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INTEGRATED CIRCUITS
DATA SHEET
TDA1310A Stereo Continuous Calibration DAC (CC-DAC)
Preliminary specification Supersedes data of TDA1310; TDA1310T July 1993 File under Integrated Circuits, IC01 May 1994
Philips Semiconductors
Philips Semiconductors
Preliminary specification
Stereo Continuous Calibration DAC (CC-DAC)
FEATURES * Space saving package DIL8 or SO8 * Low power consumption * Wide dynamic range (16-bit resolution) * Continuous Calibration (CC) concept * Easy application: - Single 3 to 5 V supply rail - Output current and bias current are proportional to the supply voltage * Fast settling time permits 2x, 4x and 8x oversampling (serial input) or double speed operation at 4x oversampling * Internal bias current ensures maximum dynamic range * Wide operating temperature range (-40 t +85 C) * Compatible with most current Japanese input formats: - Time multiplexed - Two's complement - TTL * No zero-crossing distortion. ORDERING INFORMATION PACKAGE TYPE NUMBER PINS TDA1310A TDA1310AT 8 8 PIN POSITION DIL8 SO8 MATERIAL plastic plastic GENERAL DESCRIPTION
TDA1310A
The TDA1310A is a device of a new generation of Digital-to-Analog Converters (DACs) which embodies the innovative technique of Continuous Calibration. The largest bit-currents are repeatedly generated by one single current reference source. This duplication is based upon an internal charge storage principle having an accuracy insensitive to ageing, temperature and process variations. The TDA1310A is fabricated in a 1.0 m CMOS process and features an extremely low power dissipation, small package size and easy application. Furthermore, the accuracy of the intrinsic high coarse-current combined with the implemented symmetrical offset decoding method precludes zero-crossing distortion and ensures high quality audio reproduction. Therefore, the CC-DAC is eminently suitable for use in (portable) digital audio equipment.
CODE SOT97DE SOT96AG
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Philips Semiconductors
Preliminary specification
Stereo Continuous Calibration DAC (CC-DAC)
QUICK REFERENCE DATA SYMBOL VDD IDD IFS (THD+N)/S PARAMETER supply voltage supply current full scale output current total harmonic distortion plus noise-to-signal ratio VDD = 5 V at code 0000H VDD = 5 V VDD = 3 V at 0 dB signal level at -60 dB signal level at -60 dB signal level; A-weighted at -60 dB signal level; A-weighted; R3 = R4 = 11 k; (see Fig.1); IFS = 2 mA S/N signal-to-noise ratio at bipolar zero current settling time to 1 LSB input bit rate at data input clock frequency at clock input BCK full scale temperature coefficient at analog outputs (IOL; IOR) operating ambient temperature total power dissipation VDD = 5 V at code 0000H VDD = 3 V at code 0000H A-weighted at code 0000H A-weighted; IFS = 2 mA; R3 = R4 = 11 k; see Fig.1 CONDITIONS 3 - 0.9 - - - - - - - - MIN. 5.0 3.0 1.0 0.6 -65 0.05 -30 3 -33 2.2 1.7 TYP.
TDA1310A
MAX. 5.5 4.0 1.1 - -61 0.08 -24 6 - - -
UNIT V mA mA mA dB % dB % dB % %
86 - - - - -
92 95 0.2 - - 400 x 10-6
- - - 18.4 18.4 -
dB dB s Mbits/s MHz
tCS BR fclk TCFS
Tamb Ptot
-40 - -
- 15 6.0
+85 20 -
C mW mW
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Philips Semiconductors
Preliminary specification
Stereo Continuous Calibration DAC (CC-DAC) TDA1310A
BLOCK DIAGRAM
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Fig.1 Block diagram.
Philips Semiconductors
Preliminary specification
Stereo Continuous Calibration DAC (CC-DAC)
PINNING SYMBOL BCK WS DATA GND VDD IOL Iref IOR PIN 1 2 3 4 5 6 7 8 DESCRIPTION bit clock input word select input data input ground supply voltage left channel output reference input right channel output
TDA1310A
Fig.2 Pin configuration. FUNCTIONAL DESCRIPTION The basic operation of the continuous calibration DAC is illustrated in Fig.3. The figure shows the calibration and operation cycle. During calibration of the MOS current source (Fig.3a) transistor M1 is connected as a diode by applying a reference current. The voltage Vgs on the intrinsic gate-source capacitance Cgs of M1 is then determined by the transistor characteristics. After calibration of the drain current to the reference value Iref, the switch S1 is opened and S2 is switched to the other position (Fig.3b). The gate-to-source voltage Vgs of M1 is not changed because the charge on Cgs is preserved. Therefore, the drain current of M1 will still be equal to Iref and this exact duplicate of Iref is now available at the OUT terminal. The 32 current sources and the spare current source of the TDA1310A are continuously calibrated (see Fig.1). The spare current source is included to allow continuous converter operation. The output of one calibrated source is connected to an 11-bit binary current divider consisting of 2048 transistors. A symmetrical offset decoding principle is incorporated and arranges the bit switching in such a way that the zero-crossing is performed only by switching the LSB currents. The TDA1310A (CC-DAC) accepts serial input data formats of 16-bit word length. Left and right data words are time multiplexed. The most significant bit (bit 1) must always be first. The input data format is shown in Figs 4 and 5. With a HIGH level on the word select input (WS), data is placed in the left input register, with a LOW level on the WS input, data is placed in the right input register (see Fig.1). The data in the input registers are simultaneously latched in the output registers which control the bit switches.
(1) IFS = GFS x Iref and Ibias = Gbias x Iref
An internal bias current Ibias is added to the full scale output current IFS in order to achieve the maximum dynamic range at the outputs OP1 and OP2 in Fig.1. The reference input current Iref controls with gain GFS, the current IFS which is a sink current and with gain Gbias the Ibias which is a source current(1). The current Iref is proportional to VDD so the IFS and the Ibias will be proportional to VDD as well(2) because GFS and Gbias are constant. The reference voltage Vref in Fig.1 is 23VDD. In this way maximum dynamic range is achieved over the entire power supply voltage range. The tolerance of the reference input current in Fig.1 depends on the tolerance of the resistors R3, R4 and Rref(3).
(2) ------------- = ---------- = -------------
V DD1 V DD2
I FS1 I FS2
I bias1 V DD
I bias2
(3) I ref = I ref - ------------------------------------------------------------------------------------------------R3 + R3 + R4 + R4 + R + R
ref
ref
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Philips Semiconductors
Preliminary specification
Stereo Continuous Calibration DAC (CC-DAC)
Calibration principle
TDA1310A
a.
a. Calibration. b. Operation.
b.
Fig.3 Calibration principle.
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD Tstg Txtal Tamb Ves supply voltage storage temperature maximum crystal temperature operating ambient temperature electrostatic handling note 1 note 2 Notes 1. Human body model; C = 100 pF; R = 1500 ; 3 zaps positive and negative. 2. Machine model; C = 200 pF; L = 0.5 H; R = 10 ; 3 zaps positive and negative. THERMAL CHARACTERISTICS SYMBOL Rth j-a DIL8 SO8 PARAMETER thermal resistance from junction to ambient in free air 100 210 K/W K/W VALUE UNIT PARAMETER CONDITIONS - -55 - -40 -2000 -200 MIN. 6 +150 +150 +85 +2000 +200 MAX. V C C C V V UNIT
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Philips Semiconductors
Preliminary specification
Stereo Continuous Calibration DAC (CC-DAC)
CHARACTERISTICS VDD = 5 V; Tamb = 25 C; measured in Fig.1; unless otherwise specified. SYMBOL Supply VDD IDD SVRR |IIL| |IIH| fclk BR fWS tr tf tCY tBCKH tBCKL tSU;DAT tHD:DAT tHD:WS tSU;WS supply voltage supply current at code 0000H supply voltage ripple rejection note 1 3.0 - - - - - - - - - 54 15 15 12 2 2 12 5.0 3.0 30 - - - - - - - - - - - - - - PARAMETER CONDITIONS MIN. TYP.
TDA1310A
MAX.
UNIT
5.5 4.0 -
V mA dB A A MHz Mbits/s kHz
Digital inputs; pins WS, BCK and DATA input leakage current LOW input leakage current HIGH clock frequency bit rate data input word select input frequency VI = 0 V VI = 5 V 10 10 18.4 18.4 384
Timing (see Fig.4) rise time fall time bit clock cycle time bit clock pulse width HIGH bit clock pulse width LOW data set-up time data hold time to bit clock word select hold time word select set-up time 12 12 - - - - - - - ns ns ns ns ns ns ns ns ns
Analog input; pin Iref Rref reference resistor see Fig.1 7.4 - 2.0 0.9 - 643 11.9 8.48 11.0 - - 1.0 400 x 714 13.2 9.42 10-6 14.6 k
Analog outputs; pins IOL and IOR RES VDCC IFS TCFS Ibias GFS Gbias resolution DC output voltage compliance full-scale current full-scale temperature coefficient bias current reference input current to full scale output current gain reference input current to bias current gain 16 VDD - 1 1.1 - 785 14.5 10.36 A bits V mA
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Philips Semiconductors
Preliminary specification
Stereo Continuous Calibration DAC (CC-DAC)
SYMBOL (THD+N)/S PARAMETER total harmonic distortion plus noise-to-signal ratio CONDITIONS at 0 dB signal level; note 2 at -60 dB signal level; note 2 at -60 dB signal level; A-weighted; note 2 at -60 dB signal level; A-weighted; note 2; R3 = R4 = 11 k; see Fig.1; IFS = 2 mA at 0 dB signal level; f = 20 Hz to 20 kHz tcs cs |IO| |td| S/N current settling time to 1 LSB channel separation unbalance between outputs IOL and IOR time delay between outputs IOL and IOR signal-to-noise ratio at bipolar zero A-weighted at code 0000H note 1 - - - - - - - MIN. -65 0.05 -30 3 -33 2.2 1.7 TYP.
TDA1310A
MAX. -61 0.08 -24 6 - - -
UNIT dB % dB % dB % %
- - - 86 - - 86
-65 0.05 0.2 95 0.2 0.2 92 95
-61 0.08 - - 0.3 - - -
dB % s dB dB s dB dB
A-weighted; IFS = 2 mA; - R3 = R4 = 11 k; see Fig.1 Notes 1. Vripple = 1% of supply voltage; fripple = 100 Hz. 2. Measured with 1 kHz sine wave generated at sampling rate of 192 kHz.
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Philips Semiconductors
Preliminary specification
Stereo Continuous Calibration DAC (CC-DAC)
TDA1310A
Fig.4 Timing and input signals.
Fig.5 Format of input signals.
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Philips Semiconductors
Preliminary specification
Stereo Continuous Calibration DAC (CC-DAC)
APPLICATION INFORMATION
TDA1310A
Remark: the graphs are constructed from average measurement values of a small amount of engineering samples, therefore no guarantee for typical values is implied.
Measured with a 1 kHz sinewave generated at a sample frequency (fs) = 192 kHz. (1) Measured within the specified operation supply voltage range (3 to 5.5 V). (2) Measured outside the specified operating supply voltage range (2 to 3 V and 5.5 to 6 V).
Measured with a 1 kHz sinewave generated at a sample frequency (fs) = 192 kHz.
Fig.6
Total harmonic distortion as a function of supply voltage (4fs).
Fig.7
Total harmonic distortion as a function of signal level (4fs).
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Philips Semiconductors
Preliminary specification
Stereo Continuous Calibration DAC (CC-DAC)
TDA1310A
(1) Measured including all distortion plus noise at a signal level of -60 dB. (2) Measured including all distortion plus noise at a signal level of 0 dB.
Fig.8 Total harmonic distortion as a function of frequency (4fs).
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Philips Semiconductors
Preliminary specification
Stereo Continuous Calibration DAC (CC-DAC)
PACKAGE OUTLINES
TDA1310A
handbook, full pagewidth
9.8 9.2
8.25 7.80
seating plane
3.2 max 4.2 max
3.60 3.05
0.51 min
1.15 max
2.54 (3x) 1.73 max
0.53 max
0.254 M
0.38 max 7.62 10.0 8.3
MSA252 - 1
8
5
6.48 6.20
1
4
Dimensions in mm.
Fig.9 Plastic DIL, 8-pin (DIL8).
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Philips Semiconductors
Preliminary specification
Stereo Continuous Calibration DAC (CC-DAC)
TDA1310A
andbook, full pagewidth
5.0 4.8
4.0 3.8
A
S
0.1 S
6.2 5.8
0.7 0.3
8
5 1.45 1.25
0.7 0.6
0.25 0.19
1.75 1.35
1 pin 1 index
4
0.25 0.10 detail A
1.0 0.5
0 to 8
o
MBC180 - 1
1.27
0.49 0.36
0.25 M (8x)
Dimensions in mm.
Fig.10 Plastic SO, 8-pin (SO8).
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Philips Semiconductors
Preliminary specification
Stereo Continuous Calibration DAC (CC-DAC)
SOLDERING Plastic dual in-line packages BY DIP OR WAVE The maximum permissible temperature of the solder is 260 C; this temperature must not be in contact with the joint for more than 5 s. The total contact time of successive solder waves must not exceed 5 s. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified storage maximum. If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. REPAIRING SOLDERED JOINTS Apply a low voltage soldering iron below the seating plane (or not more than 2 mm above it). If its temperature is below 300 C, it must not be in contact for more than 10 s; if between 300 and 400 C, for not more than 5 s. Plastic small-outline packages BY WAVE During placement and before soldering, the component must be fixed with a droplet of adhesive. After curing the adhesive, the component can be soldered. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder bath is 10 s, if allowed to cool to less than 150 C within 6 s. Typical dwell time is 4 s at 250 C.
TDA1310A
A modified wave soldering technique is recommended using two solder waves (dual-wave), in which a turbulent wave with high upward pressure is followed by a smooth laminar wave. Using a mildly-activated flux eliminates the need for removal of corrosive residues in most applications. BY SOLDER PASTE REFLOW Reflow soldering requires the solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the substrate by screen printing, stencilling or pressure-syringe dispensing before device placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt, infrared, and vapour-phase reflow. Dwell times vary between 50 and 300 s according to method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 min at 45 C. REPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING
IRON OR PULSE-HEATED SOLDER TOOL)
Fix the component by first soldering two, diagonally opposite, end pins. Apply the heating tool to the flat part of the pin only. Contact time must be limited to 10 s at up to 300 C. When using proper tools, all other pins can be soldered in one operation within 2 to 5 s at between 270 and 320 C. (Pulse-heated soldering is not recommended for SO packages.) For pulse-heated solder tool (resistance) soldering of VSO packages, solder is applied to the substrate by dipping or by an extra thick tin/lead plating before package placement.
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Philips Semiconductors
Preliminary specification
Stereo Continuous Calibration DAC (CC-DAC)
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
TDA1310A
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
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Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, International Marketing and Sales, Building BAF-1, P.O. Box 218, 5600 MD, EINDHOVEN, The Netherlands, Telex 35000 phtcnl, Fax. +31-40-724825 SCD31 (c) Philips Electronics N.V. 1994
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
513061/1500/02/pp16 Document order number: Date of release: May 1994 9397 733 00011
Philips Semiconductors

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